Encyclopedia of RF and Microwave Engineering , 6-Volume Set by Kai Chang

By Kai Chang

RF and Microwave Engineering is likely one of the quickest progress components of the previous decade and may most likely stay a truly energetic quarter of study and alertness in a wide number of fields. The six quantity set of Encyclopedia of RF and Microwave Engineering illustrates how this box has been the major to allowing know-how liable for the exceptional progress of instant communications. This set additionally examines how RF and microwave engineering keeps to have nice impression because the expertise at the back of such very important functions as radar, distant sensing, handheld remote control, sensors, navigation, surveillance, digital war, radiometers, plasma learn, and imaging.

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  • AAP Awards for Excellence in expert and Scholarly Publishing, 2006

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Extra resources for Encyclopedia of RF and Microwave Engineering , 6-Volume Set

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Such systematic error introduces pattern noise in the form of spurious tones that appear as harmonics of the input signal frequency. Since harmonics are most undesirable in telecommunications and audio applications, techniques are needed to alleviate this problem. A dynamic element matching (DEM) techniques provide one such solution. Various DEM algorithms have been proposed in the literature offering different flavors, but their end goal is the same [14–17]. The main purpose of the DEM algorithm is to provide either random scrambling or permutation of the current sources such that the amount of error introduced by the D/A converter is not the same for the same input applied at two different time instants.

ViÀ1 is the residue output of the previous stage (for the first stage, the input is V0 ¼ Vin. The output residue voltage of the stage i is then passed to the next stage i þ 1, and the same operation continues. Ideally, we expect the residue output voltage to be Vi ¼ 2ViÀ1 À Di Vref 2ðni ÀkÞ DSniÀ1 þ k Vref k¼1 ð10Þ The ideal residue output of a one-bit pipeline stage is shown in Fig. 22, assuming { À Vref, þ Vref} as the resolvable input range. We see that as input is increased from À Vref to þ Vref, the output spans the full scale twice, once for the output Di ¼ À 1 and for the output Di ¼ þ 1.

As mentioned earlier, the complexity of the pipeline, measured in the number of stages, scales linearly with the desired resolution and therefore pipelined A/D converters show substantial power and area savings for high-resolution applications at high speed. In the pipeline architecture, as in all multistage ADC, the most significant bits are resolved by the stages earlier in the pipeline and the least significant bits are resolved later in the pipeline. A simple example for a pipeline would be a 1-bit per stage architecture (ni ¼ 1).

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