Emerging Memory Technologies: Design, Architecture, and by Yuan Xie (auth.), Yuan Xie (eds.)

By Yuan Xie (auth.), Yuan Xie (eds.)

This publication explores the layout implications of rising, non-volatile reminiscence (NVM) applied sciences on destiny desktop reminiscence hierarchy structure designs. because NVM applied sciences mix the rate of SRAM, the density of DRAM, and the non-volatility of Flash reminiscence, they're very beautiful because the foundation for destiny common thoughts. This ebook offers a holistic viewpoint at the subject, protecting modeling, layout, structure and purposes. the sensible info integrated during this ebook will let designers to use rising reminiscence applied sciences to enhance considerably the performance/power/reliability of destiny, mainstream built-in circuits.

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Extra info for Emerging Memory Technologies: Design, Architecture, and Applications

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Furthermore, the default setting of including sense amplifiers in each subarray can cause a dominant portion of the total array area. As a result, for high-density memory Fig. 9 An example of mat using internal sensing and H-tree routing 28 X. Dong et al. Fig. 10 An example of mat using external sensing and bus-like routing module designs, NVSim provides an option of moving the sense amplifiers out of the subarray and using external sensing. In addition, a bus-like routing organization is designed to associate with the external sensing scheme.

10. The wire partitioning rule described in Sect. 5 can also be applied to the bus-like organization with a few extensions. For example, a multiplexing node with a fanout of N decrements the number of address wires by log2 N instead of 1; a merging node with a fanout of N divides the number of distributed data wires by N instead of 2. Furthermore, the default setting of including sense amplifiers in each subarray can cause a dominant portion of the total array area. As a result, for high-density memory Fig.

15 Conceptual view of a cross-point cell array without diode (0T1R) and its connected word lines and bit lines Compared to MOS-accessed cells, cross-point cells have worse cell isolation but provide a way of building high-density memory chip because they have much smaller cell sizes. In some cases, the cross-point cell size is constrained by the diode due to limited current density, and NVSim allows the user to override the default 4F 2 setting. 3 NAND String Cell NAND string cells are particularly modeled for NAND flash.

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